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The Debate Over Processor Speed

A perennial topic at the International Solid State Circuits Conference is the debate between what have been termed the architects and the speed demons. These two camps, one emphasizing simple logic circuitry to increase clock frequency and the other pushing complex circuitry to increase the amount of work done in a clock cycle, have been fighting since the days of the first RISC CPUs over what was the best approach to increasing processor performance.

This year's incarnation of the debate took place at a Tuesday evening session of the ISSC Conference entitled: "Processors and Performance: When do GHz Hurt?"

With so few viable processor design teams remaining in the industry, there is always the risk that such a panel will devolve into a round of Intel-bashing, and that's pretty much what happened this time.

Panel chair Shannon Morton, staff engineer at Icera Semiconductor, observed that the increase in clock frequency that has led us to 3 GHz CPUs had not come just from process scaling. There has also been a consistent and aggressive reduction in the number of fan-out-of-four gate delays per logic stage. This has contributed a significant portion of the reduction in cycle times.

Morton then framed the discussion with two broad questions. First, what is the end customer's perception of performance? Second, should we continue to focus on clock frequency in our pursuit of the customer's dollars?

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