SANTA CLARA, Calif. Panelists at the Multicore Expo here Wednesday (March 22) generally agreed that multitasking and multiprocessing have bright futures, although they identified some challenges as well. One of those challenges is the difficulty of programming next-generation multicore ICs.
Multithreading, said Michael Uhler, CTO of MIPS Technologies, provides an increase in performance without compromising power. He said the number of cores may be reduced as cores take on more capabilities, including multithreading. That's consistent with MIPS' position in February, when the company rolled out its MPS34K, a "virtual CPU" core that MIPS believes can forestall the need to move to multicore designs for some multimedia and network applications.
Heterogenous or asymmetric multiprocessing (AMP) multicore systems-on-chip (SoCs) are being built because they have lower bill of materials costs, Uhler said. "It wouldn't surprise me to see SMP [symmetric multiprocessing] on the host processor, with the system remaining AMP because of the BOM cost," he said.
John Goodacre, program manager for multiprocessing at ARM Ltd., also noted the difference between multiprocessing in SoCs and on the host processor. "There's a lot of momentum in looking at the host node as multicore," he said.
One of the challenges for AMP designs, he said, is the number of processors people are trying to work with. "The programmer is limited by the number of concepts he can hold in his head," Goodacre said. "Are you going to have 20 to 30 accelerators from different vendors? No the licensing department isn't going to like that very well."
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