P4: Programming the Network's Forwarding Plane

The pace of innovation in networking world is increasing with the immense growth in IoT devices, increasing data traffic, new protocols, and private and public clouds. The future of networking has gone beyond that of separating data and control planes for SDN, to programming the forwarding logic deep within the ASIC. Technology is now moving from a traditional fixed architecture silicon switch to flexible programmable switches. New programmable ASICs support custom protocols, as well as protocols of today and future.

To take full advantage of this flexibility requires a new higher level, domain-specific language to simplify the writing of forwarding plane. Each ASIC manufacturer has to come up with their own custom language which is more of dependent on the hardware architecture. Porting of forwarding plane logic from one manufacturer of networking ASIC to another will require a lot of efforts and is really painful. This generates a need of standard language that is independent of underlying hardware and protocols.

That’s where P4 (Programming Protocol-Independent Packet Processors) comes in. P4 is an open source, domain-specific programming language designed specifically for programming reconfigurable networking pipelines. The P4 language is public and developed by the p4.org consortium, which includes various companies in the area of networking, cloud systems, and academic institutions. Initially, P4 was aimed at data plane programming of network switches. Its scope has broadened to cover programmable network elements including hardware or software, network interface cards, and other packet processing systems. 

P4 Compiler: How P4 is Target Independent

From the past few years, it has been clear that packet processed by the data plane in any networking devices can roughly be in three basic stages. 1) Parser block: Responsible for packet identification and extraction, 2) Control block: Responsible for match + action and 3) DeParser: Responsible to form the desired egress packet.

Networking chips are being built this way and are protocol independent. P4 is the language that can compile for any target device to specify how the packets can be processed in a data plane. The architecture of P4 Compiler helps to make it target independent by separating language and the target model. P4 has a frontend open source and a backend loose to make it independent of target. Each chip vendor can implement its own compiler backend to map to their hardware architecture. The architecture of P4 (see figure) also helps to insulate hardware details by allowing chip companies to define their own model and then write the P4 backend to support the same.

Each chip manufacturer just needs to have a P4 compiler tool chain compatible with their hardware, users can write their own P4 program independent from the vendor’s dependency, compile and run without compromising speed. The user only needs to focus on actual packet processing logic without worrying on underlying hardware. The compiler will generate runtime code for your hardware. The figure below shows the core components provided by P4 for data plane programming.

How is P4 beneficial?

P4 brings many benefits including:

There are, however, some challenges that might prevent fully achieving these benefits. One point to keep in mind is that custom proprietary languages have more control over programmable networking hardware. P4₁₆, the 2016 revision of the P4 language, does support external methods to suffice such custom hardware specific requirements, but this makes P4 less portable.

Additionally, features like Hash, ECMP, multicast, broadcast, mirroring, queuing, scheduling, and Checksum are very much hardware dependent. To address all targets using Generic P4 and getting full access to hardware is difficult.

There are limited means of communication between control plane and data plane in P4. So, there is no support for generating the new packets.

That said, P4 opens up many opportunities and changes the way networking chips are designed. P4 architecture gives a sample model and idea to design a fully programmable chip. Moving forward all traditional switches will be soon converted into programmable switches with fully software defined data and control plane.

About the author: Komal Shah is associated with VOLANSYS Technologies as a Senior Engineer with 3+ years of experience in development of Software Development Kit (SDK) for reconfigurable networking switches. She has good hands-on working with programmable Parser, P4 Compiler back-end development and data plane pipeline programming.