Kurt Marko

Contributing Editor

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Where the Cloud Touches Down: Simplifying Data Center Infrastructure Management

Thursday, July 25, 2013
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In most data centers, DCIM rests on a shaky foundation of manual record keeping and scattered documentation. OpManager replaces data center documentation with a single repository for data, QRCodes for asset tracking, accurate 3D mapping of asset locations, and a configuration management database (CMDB). In this webcast, sponsored by ManageEngine, you will see how a real-world datacenter mapping stored in racktables gets imported into OpManager, which then provides a 3D visualization of where assets actually are. You'll also see how the QR Code generator helps you make the link between real assets and the monitoring world, and how the layered CMDB provides a single point of view for all your configuration data.

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Cavium SoCs Promise Fast, Cheap IT Hardware

Cavium is announcing a new system on a chip (SoC), the OCTEON III, that targets the network equipment market for small and midsize companies. Cavium has been an under-the-radar arms merchant to the network equipment market for years, but its new embedded SoC will get the attention of a wider audience of system builders.

The OCTEON III should ultimately translate to a new generation of entry-level network and storage appliance hardware that rivals the features and performance of today's mid-range products that have price tags one or two orders of magnitude higher.

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SoCs combine multiple processing cores, two or three layers of cache, plus general-purpose memory and several I/O subsystems onto a single piece of silicon. Today, SoCs provide much of the computational abundance in today's smartphones and tablets. But embedded SoCs with more, higher performing cores are being mated to network-specific modules such as packet processors, 10-Gb Ethernet PHYs, deep packet inspection (DPI) engines, cryptographic accelerators and RAID processors.

Companies such as Broadcom, Freescale, LSI and Marvell are commonly associated with the guts of infrastructure equipment. But little (and little-known) Cavium, whose market cap is a mere fraction of its better-known competitors, is unleashing a family of SoCs that could soon leave the big boys eating dust.

[For more on the development of merchant silicon and its impact on networking, check out Merchant Silicon About to Get Smarter]

Cavium claims its OCTEON III processors are the first quad-core, 64-bit SoCs with full OS virtualization support, advanced security hardware, crypto and network processing subsystems, and embedded high-performance I/O modules. All this comes on a device expected to cost $20 to $50 in volume--that is, the sweet spot for hardware targeting consumer, SOHO and SMB price points.

Unlike most embedded systems jumping on the ARM bandwagon, Cavium is sticking with the MIPS architecture it's well familiar with. In fact, according to the company, Cavium designs the cores in-house instead of using a MIPS-licensed macro cell.

Sticking with MIPS means Cavium's next-generation SoCs will beat ARM licensees to 64 bits and include hardware virtualization support, allowing applications to be sandboxed in their own VM.

Other features sure to pique the interest of network equipment designers include hardware memory management, an embedded load balancer that optimizes core utilization, an advanced crypto engine supporting 2K and 4K long keys (an increasingly important feature as more sites such as Google start using long SSL certificates), one or more hardware DPI engines, a packet processor supporting QoS, TCP offload, packet ordering, scheduling and packet synchronization, and hardware RAID (for storage appliances).

It also includes a wide variety of I/O modules including SATA 3.0, PCIe 3.0, single 10 GbE or eight 1GbE and USB 3.0. All this runs at core speeds of up to 1.6 GHz while burning under 7W.

In sum, it's everything you need to build a range of products from 802.11ac APs and UTM appliances to converged iSCSI/NAS storage appliances.

Of course, what makes such integration possible is Cavium's move to a next-generation 28nm process node. This offers over five times the density of the 65nm process used for the previous-generation OCTEON, and allows it to pack three times the performance into the same power envelope.

Cavium also offers a comprehensive software stack, which could simplify the work of system builders. The stack includes turnkey applications for network UTM gateways, wireless APs and networked storage. The foundation is a hardened embedded Linux MontaVista distro supporting KVM, Linux Containers and LibVirt with a suite of tracing and debugging tools and code modules for common network functions, including SSL, IPSec and DPI.

Cavium builds two turnkey applications on this software foundation. Its network security platform features protocol detection, URL filtering, anti-malware, IPS and application QoS targeting next-generation entry-level UTM appliances with either 1x10-GbE or 8x1-GbE interfaces and processing at least 8 million packets per second, tens of thousands of DPI flows and thousands of NAT'ed firewall sessions.

The same SoC can be used with Cavium's storage software that supports systems with the same 1x10 or 8x1 GbE network ports, along with two SATA 3 and two USB 3 interfaces, and features over 200 MB/sec NAS performance, iSCSI target, hardware-accelerated dedupe and multiple local, encrypted file systems. In either case, these are not features and performance profiles you expect to see in a $200 to $400 device.

This sort of price/performance ratio is coming sooner than you think. Cavium has all the OCTEON III hardware design materials and software available now, and is currently producing the initial batch of chips. It expects to ship samples in the middle of the third quarter with production quantities in the fourth quarter.

Given that much of the design, test and debugging work can be done using Cavium's prior-generation OCTEON II, look for actual systems using the technology early next year. With this chip under its belt, Cavium plans to scale its technology to as many as 48 cores with larger caches and more I/O interfaces to target higher-end systems.

Kurt Marko is an IT pro with broad experience, from chip design to IT systems.

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