The company says its HPFC-5600 Tachyon DX2+ [ed. note: well that just rolls off the tongue] Fibre Channel controller is the first in the industry to include error detection code (EDC), which detects data corruption in storage subsystems.
"We're solving the problem of data integrity in hardware, so it's much faster than alternative approaches," says Erik Ottem, marketing director for Agilent's storage networking division.
EDC, which Agilent helped develop, is a double-bit error correction algorithm, meaning that it's much faster than single-bit algorithms. Moreover, unlike current error-correction techniques -- including those used in its own previous generations of the Tachyon chip -- Agilent says EDC is optimized to run in hardware and that it's well integrated at the system level with other components in a storage subsystem.
The HPFC-5600 uses EDC to flag the data error and alert the memory subsystem's software driver. That driver can then take corrective measures to recover the I/O, Agilent says. The chip's EDC algorithm maintains the SCSI command structure and architecture model, and enables EDC to stay with the data for its entire life within the storage array.