The new non-volatile PCM technology combines many of the benefits of today's memory types, but for the first time researchers have demonstrated a 64Mb test chip that enables the ability to stack, or place, multiple layers of PCM arrays within a single die. These are findings that pave the way for building memory devices with greater capacity, lower power consumption and optimal space savings for random access non-volatile memory and storage applications.
"The results are extremely promising," said Greg Atwood, senior technology fellow at Numonyx. "They show the potential for higher density, scalable arrays and NAND-like usage models for PCM products in the future. This is important as traditional flash memory technologies face certain physical limits and reliability issues, yet demand for memory continues to rise in everything from mobile phones to data centers."
Intel and Numonyx have been researching new memory technologies and resistive materials over the past ten years as part of an effort to identify next generation solid state (SSD) memory alternatives. "What we wanted to do was to be able to stack multiple cross point memory on top of CMOS at the backend of the process, but this was extremely hard to do," said Al Fazio, Intel fellow and director, memory technology development. "To do this, we employed a thin film, two-terminal OTS (Ovonic Threshold Switch) selector that matched the physical and electrical properties for phase change memory scaling." With the compatibility of thin-film PCMS (phase change memory and switch), multiple layers of cross point memory arrays are now possible. Once integrated together and embedded in a true cross point array, layered arrays are then combined with CMOS circuits for decoding, sensing and logic functions.
The multi-stacked PCMS combines elements of RAM and NAND/NOR solid state memory that could make it a candidate to one day blend these different memory classes into a world-class storage solution. "NAND and NOR memory operate on blocks of data, but the PCM memory has the ability to alter a single bit of data, as RAM does," said Atwood. PCM also employs low voltage technology, in contrast to NAND, which uses an electrical charge to distinguish a "0" from a "1" as it reads memory. Because PCM is low voltage and reads the "0s" and "1s" of memory by detecting the difference between crystalline and amorphous material states of storage, it does not require the high voltages that NAND consumes. This makes PCM theoretically more scalable, and also less power-consumptive. To illustrate, NAND voltages can reach over 20 volts. This makes it hard to scale NAND below 20 nanometers.
PCM's comparatively lower voltage allows it to scale down to five nanometers or lower and still deliver a stable state. The scalability potential of PCM, coupled with PCM's ability to multi-stack as many as four layers of memory in practice, with a theoretical boundary of unlimited layers, holds promise that the technology will exceed both NAND and NOR memory in economy of cost and in scalability. Cost and scalability have been barriers to enterprise adoption of NAND and NOR solid state memory.