Like the previous two generations of Cortina EDC devices, the CS4340 PHY maximizes data center, server, and switching efficiency with its low power, low latency implementation of the PHY functionality. Due to its hybrid DSP analog architecture, the CS4340 PHY has latency of less than one nsec. Competing solutions can be anywhere from 80 to 240 nsec.
The CS4340 PHY versatile design and industry leading performance with full compliance to industry standards allows it to be used in either a standalone operation or programmed to optimize application specific performance and power. Its interoperability has been proven at industry plugfest, such as Ethernet Alliance's SFP+ Direct Attach Copper interoperability tests performed at UNH-IOL. By exceeding the industry's standards requirements, the CS4340 PHY increases application margins and link distances.
"EDC enabled 10G and 40G links are now a reality; system architects need standard compliant devices that can be deployed in datacenter switches, core routers, and KR Backplanes," said Scott Feller, product line director at Cortina. "With our proven industry leading solution, standards compliance, and small form factor, the CS4340 PHY meets these needs and enables a single system design that addresses the complete spectrum of applications."
The CS4340 PHY functionality supports four full duplex 10G links. Both transmit and receive paths include Clock and Data Recovery (CDR) circuits. The device has a wide operating frequency range covering 1GbE, 1G FC, 2G FC, 4G FC, 8G FC, SONET (9.5 - 11.3G), and 10GbE. EDC capability allows the device to operate with linear SFP+ optical modules to support 10Gbase-LRM and Direct Attach Copper. The transmit path includes a 10Gbase-KR compliant 3 tap transmit pre-emphasis capability. The transmit pre-emphasis in conjunction with the receive EDC enables the device to support 10Gbase-KR, 8G FC and telecom backplane applications. The device is fully autonomous and does not require external processors to control the initial convergence or the dynamic adaption of the dispersion compensation. In addition, the device includes extensive debug features and I/Os for device monitoring and control.