Recent news of the HyperTransport Technology Consortium draws attention to an increasingly public duel between two technologies aimed at speeding up throughput on today's high-speed networks (see 'HyperTransport' Consortium Grows).
Those two technologies are HyperTransport and RapidIO (which has its own banner group, the RapidIO Trade Association). Both are chip-to-chip interconnection techniques aimed at ensuring that the inner workings of network and storage gear won't wind up being a bottleneck as carriers move to ever faster services.
A quick backgrounder: Today, networking devices that deploy multiple processors typically rely on the PCI bus or similar techniques to process information, such as packet lookups, inside a box. These technologies have maximum data rates of about 1 Gbit/s today (with exceptions), and they don't support varying amounts of bandwidth in one device.
But speed and bandwidth flexibility will be required of mainstream storage and networking gear as networks move to 10 Gbit/s data rates and beyond. For example, OC192 network processors supporting functions for next-generation Sonet switches will need to get lots of data on and off their chips fast.
Enter HyperTransport and RapidIO, which were devised by different vendors to speed up devices based on their chips. Simply put, both are ways of ensuring that complex, multiprocessor boxes will perform as well as the high-speed networks they're meant to run on.
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