Now, EMC is accusing HDS of upwardly revising the maximum cache bandwidth it can provide, to 10.6 GByte/s, after the DMX's launch. Cache bandwidth is the total throughput that's achievable between the back-end disks and the front-end external ports of a system. According to EMC, the Hitachi Lightning 9980V supports a maximum of 3.2 GByte/s, compared with the DMX 2000 at 16 GByte/s.
"HDS has four cache regions per system and is therefore only capable of performing four concurrent DRAM [dynamic random access memory] transfers at 800 MByte/s each," says EMC spokesman A.J. Ragosta.
But HDS says that's a blatant misrepresentation of its Hi-Star crossbar switching architecture. Here's Hitachi's math: It claims each of the Lightning 9980V's four cache switches (CSW) has eight ports, for a total of 32 data paths. Each of those 32 paths is clocked at 166 MHz, yielding 332 MByte/s per path for a total of 10.6 GByte/s. "EMC's logic only applies to a bus-based architecture," says an HDS insider.
Duplessie, however, verifies EMC's interpretation. "When HDS came out originally [with the Lightning 9900 in June 2000], they started making performance claims of 6.4 GByte/s which is how fast you can go to the cache," he says. "In that sense, EMC can go 64 GByte/s to the cache. In the real world, you have to go through the cache."
HDS says it's sticking to its claims. "We stand by our numbers, and we've proven our performance and capabilities to our customers," says spokeswoman Jodi Reinman. She also notes that EMC refuses to publish performance figures for its systems using the Storage Performance Council's benchmark. [Ed. note: Although technically, neither has HDS, yet.]
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