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Where the Cloud Touches Down: Simplifying Data Center Infrastructure Management

Thursday, July 25, 2013
10:00 AM PT/1:00 PM ET

In most data centers, DCIM rests on a shaky foundation of manual record keeping and scattered documentation. OpManager replaces data center documentation with a single repository for data, QRCodes for asset tracking, accurate 3D mapping of asset locations, and a configuration management database (CMDB). In this webcast, sponsored by ManageEngine, you will see how a real-world datacenter mapping stored in racktables gets imported into OpManager, which then provides a 3D visualization of where assets actually are. You'll also see how the QR Code generator helps you make the link between real assets and the monitoring world, and how the layered CMDB provides a single point of view for all your configuration data.

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Thursday, August 8, 2013
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This webinar will help attendees understand the overall concept of SDN and its benefits, describe the different conceptual approaches to SDN, and examine the various technologies, both proprietary and open source, that are emerging. It will also help users decide whether SDN makes sense in their environment, and outline the first steps IT can take for testing SDN technologies.

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Intel Announces New Itanium Chips, Hints at Server Roadmap

Intel announced the Itanium 9500, or "Poulson," chips at an event co-hosted with HP in San Francisco last week. The chip is the newest in Intel's product line that targets high-end, mission-critical servers and computers. It replaces the Itanium 9300, or "Tukwila," line, which began shipping in early 2010.

The event had a bit more intrigue than most processor news events because of HP's lawsuit against Oracle, which concluded earlier this year. Oracle had declared that new versions of its database software would no longer support HP's high-end servers. These servers--including new Integrity products, also announced Tuesday--run on Itanium, which HP originated before Intel joined as a collaborator. The future of the platform seemed imperiled when HP alleged contract infringement and sued, and even the decision, which saw Oracle resume Itanium support, didn't clarify where the processor family was headed.

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On Thursday, Rory McInerney, the GM of Intel's Server Group and MC for the announcement, offered enough information to confirm Itanium will remain an ongoing project--if not also a changing one, thanks to the infusion of Xeon features, detailed below.

McInerney also verified Poulson's improvements, which were first hinted at when product details were accidently posted in July. How these benefits will stack up to competing platforms, such as IBM's recently updated Power line, remains to be seen, but it's clear that Tukwila users who upgrade their systems to Poulson should expect meaningful performance gains.

The 9500 chips trade their predecessor's 65nm architecture for 32nm technology and come in four varieties, each of which is advertised as delivering distinct cost-to-performance benefits. Depending on the model, the new iron either matches Tukwila's four cores or doubles the number to eight. Clock speeds range from 1.73 GHz to 2.53 GHz, with the top model offering a 40% boost in processing power relative to the previous generation. The chips include up to 54 Mbytes of on-die memory and enable 2-Tbyte DIMMs in a four-socket configuration. McInerney said the chips offer 33% greater bandwidth and also asserted that they draw 8% less power when active and 80% less when idle. All these features together, he says, amount to 2.4 times better performance than that of the 9300 series.

The new chips' improvements extend beyond specs and speeds. McInerney said, for example, that Poulson features thread-level parallelism, which would reduce the number of stalled instruction strings. He also touted hardware-software marriages, such as error detection that occurs in the firmware, as engines for improved system stability. Cache Safe Technology, which has migrated to Itanium from Intel's Xeon chips, received particular attention--the feature allows the CPU to recognize when memory bits fail, and to block the offending row or column from being used in the future.

Though Intel has discussed the idea for years, the porting of Xeon characteristics to Itanium portends shakeups in Intel's architecture strategy. McInerney alluded to the need for a shift throughout the presentation, including an opening portion in which he outlined the tension between x86 systems--which include the Xeon E7 family and power the most of the world's cloud offerings--and the Linux-compatible mainframe OSes that Itanium drives. "It means we want to take critical systems, consolidate them into new hardware, and engender confidence that it will be ready for the future," he said.

McInerney said that a new design process has been developed for the next Itanium iteration, code-named "Kittson." Called the "Modular Development Model," the process allows both E7 and Itanium chips to share certain components, ranging from silicon-level elements to socket compatibility. The result is that the E7 family gains upstream features while Itanium enjoys more favorable economies of scale. It also allows OEMs to develop single motherboards for both architectures. This process should improve customer choice.

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