Ottawa-based Zarlink Semiconductor has come out with a set of new timing chips designed to boost performance for SONET/SDH (Synchronous Optical Networks/Synchronous Digital Hierarchy) and PDH (Pleisiochronous Digital Hierarchy) systems.
The two chips, a DPLL (digital phase-locked loop) and APLLs (analog phase-locked loop) were developed for line cards used in both enterprise and carrier networks. According to company officials, they are designed to work together, and that by doing so they improve timing capabilities and performance while meeting system compliance requirements with substantial jitter margins.
Among the features of the Zarlink ZL 30106 DPLL are an OC-3 jitter compliance margin, hitless reference switching, reference monitoring and holdover.
The two chips, say officials, enable frequency synthesis techniques that minimize low-frequency noise. This lets network designers optimize the APLL bandwidth and improve jitter performance and error-free transmission.