Device technology is expected to make even more progress. This is why size reduction and functionality of personal devices is expected not to constitute a fundamental problem, per se. The fundamental factors limiting the design of high-capacity ubiquitous wireless systems are expected to be:

Spectrum shortage is mainly due to regulation and coordination with existing services. Device power supply technology, which is not expected to make substantial progress (1-2 orders of magnitude) in the next decade, is why power consumption has to be limited. Infrastructural investments could include both devices and fixed networks. Can all these limiting factors be set aside with no fundamental restriction on the capacity in numbers of wireless users and the user bandwidth provided? By limiting, for instance, the infrastructural investments (for example, the number of wireless access points to the fixed network), spectrum efficiency will be degraded and device power consumption will have to be increased due to higher transmitter power and increased signal processing burden due to adverse propagation conditions. The sheer numbers of radio ports and mobile devices in future high-density wireless systems will require efficient and reliable distributed network functions in order to avoid centralized system vulnerability and excess signaling data volume. Therefore, contrary to traditional network design, let’s assume that the following factors are limiting:

Main Problem Areas

The design of efficient wireless infrastructures is a truly an interdisciplinary activity–spanning services and user behavior, infrastructural economics, telecommunication analysis down to implementation issues, and device technology. The main problem areas that can be identified are discussed in the sidebar, "Major Issues."

Major Issues

In this next part of the chapter, the overall wireless system design, analog RF circuitry, and digital baseband circuitry are discussed–particularly emphasizing a single chip, the silicon Complementary Metal Oxide Semiconductor (CMOS) solution, for the mobile receiver. The discussion will focus primarily on the broadband downlink–given the high data rates, the need for low power consumption, and size in the portable unit.

Over the past several years, wireless communications have seen dramatic advances in two distinct areas. On one hand, the demand for portable voiceband services has resulted in intense research efforts to improve performance and increase capacity through digital transmission. Such systems focus on wide-area narrowband communications, providing low-bandwidth network services to individual users in a portable fashion. On the other hand, the need for more flexible computer networks has led to the advent of wireless LAN’s such as the ones discussed in the sidebar, "Wireless LANs" and Table 11—1 [1]. Such systems focus on local-area wideband communications, providing networking services to individual computers but usually not easily portable.

Wireless LANs

The distinction between these two wireless systems is rapidly blurring. As laptop computers place mobile computing resources in the hands of individuals, wireless technologies capable of providing wide-area, wideband services will clearly be needed. With this merging of computation and communications, individual users will have instantaneous and portable access to fixed information networks via a lightweight mobile unit. Furthermore, users will be capable of transferring data to other users and accessing fixed computing resources without any constraints on where or when such access takes place. As shown in Figure 11—1, the mobile unit will support a myriad of services, including full-motion digital video and high-quality audio, and combines the functionality of today’s analog mobile telephones, radio pagers, and laptop personal computers [2].

Since portability places severe constraints on the physical weight of the terminal, the available battery power is quite limited. Thus, power minimization is crucial; power reduction in both the digital and analog hardware must be achieved. To this end, the terminal should only carry the bare minimum of computing resources necessary to support its functionality. User computation should be mainly performed by large, non-portable computing facilities, with the high-speed wireless link serving as the terminal’s means of accessing the fixed computation servers and data networks. Direct point-to-point wireless communication is not allowed; the link only provides the final interface into the wired data network, much like a conventional telephone handset serves as the link into the telephony system. Whereas the capability of moving massive amounts of digital data within networks already exists, the problem of easily getting data in and out of those networks is now addressed.

Although placing all computation services back in the wired network has immediate benefits in terms of reducing power consumption, it provides another advantage: data that is highly sensitive to corruption will not be transmitted over the wireless network. Existing distributed computation environments are crucially dependent on the fact that data transmitted over the network has high integrity (bit-error rates on wired Ethernet are typically on the order of 1 per 1012 bits and further protection is gained by packet retransmit in the case of an error). However, on wireless networks this is not true; even after extensive error-correction coding, it is still difficult to attain error rates even remotely as low as this. User computation data, such as spreadsheets or simulation results or bank transfers, simply cannot be allowed to sustain any corruption. For wireless systems, this translates into an inordinate amount of transmission overhead in terms of coding and data retransmission to compensate. On the other hand, user multimedia information, such as voice and image data, is relatively tolerant of bit errors. An error in a single video frame or an audio sample will not significantly change the meaning or usefulness of the data. Thus, the portable unit described above is truly a terminal dedicated to multimedia personal communications, and not simply a notebook computer with a wireless LAN/modem attached to it.

With the shift in emphasis from computation inside the mobile unit over to communications outside, it is evident that development of a wideband link capable of supporting the required user bandwidth becomes paramount. The uplink is used only for low-rate speech and control data. Although the system is still full-duplex, this asymmetry must be accounted for in the design, as the bandwidth requirements for maintaining the uplink are thus considerably less than those for the downlink.

Broadband Spread-Spectrum Communications

Even with a reliable, guaranteed latency backbone network, the issues of user capacity and overall system bandwidth consumption still remain. With the best compression schemes developed to date, data rates in excess of 1 Mbps per user would be needed to support full-motion video. However, this data rate is not needed on a continuous basis. When regular computational tasks are being performed on compute servers back on the network (such as using a word processor or a spreadsheet), the screen changes only slightly on a frame-by-frame basis; and, over only a small region–usually on the order of a single character or a few pixels. Hence, the peak data rate required by a user may easily be much larger than the overall time-average data rate. Thus, minimizing the overall system bandwidth consumption while supporting a large number of users accessing data simultaneously is of paramount importance.

The advantages in improved spectral efficiency afforded by cellular systems have long been known. They have already been employed to a limited extent by existing analog mobile telephony systems, with cell size on the order of square kilometers. Due to the tremendous bandwidth requirements of such a portable terminal, it is inevitable that future wideband systems will exploit picocellular networks with cell sizes on the order of meters to employ as much frequency reuse as possible.

The primary interference mechanism in such a cellular transmission environment is that of multipath fading, in which the transmitted signal interferes at the receiver due to reflections off of objects. From statistical measurements [Sheng, 3], the short-range indoor channel that’s been considered has typical delay spreads ranging from 20 nsec to 60 nsec with Rician-distributed fading characteristics. This is far different from the typical outdoor large-cell transmission environment that has much more severe Rayleigh fading characteristics. Likewise, the indoor transmission environment changes far more slowly than the outdoor, given that the mobile unit will likely be stationary during use.

With this in mind, direct-sequence spread spectrum, or code-division multiple access becomes attractive for use in the downlink. It is naturally immune to multipath, since it can (with sufficient spreading) resolve the interfering multipath arrivals and combine them via a Rake Receiver (receiver having a number of individual digital channels, or tines, which can combine these channels to form a stronger received signal) as an intrinsic form of diversity. Also, CDMA can easily accommodate a wide range of user data rates by varying the transmit power for each user as a function of the required data rate. This concept of power modulation has already been exploited to improve the effective system capacity of next-generation digital cellular systems [Sheng, 3]. It is important to realize that traditional impairments of CDMA systems such as near-far interference and unsynchronized codes do not exist for the downlink, since all downlink transmissions originate from a single point–the base station. The broadcast nature of the signal, combined with the ability to resolve multipath arrivals and support variable data rates, makes CDMA extremely attractive for use in the high-performance wireless downlink in the system.

With these factors in mind, the system itself is a wideband extension of the U.S. IS-95 digital cellular CDMA standard [Sheng, 3], which utilizes a transmitted synchronization tone for timing recovery and Walsh orthogonal codes to multiplex users. A basic raw user data rate of 2 Mbps is assumed to allow a margin for channel error correction as well as the ability to explore various compression algorithms. The raw data is then modulated into a 1 Mbaud differential quadrature phase shift keying (DQPSK) symbol stream. In determining the cell size of 5 meters, a typical office environment consisting of soft-partition cubicles is assumed, with each cell typically containing 12 to 16 active users. Of those 16 users, it is assumed that approximately half are demanding the full 1 Mbaud data rate for video use, while the remainder are utilizing 128 Kbaud (256 Kbps) each for lower data rate applications such as voice or text and graphics. With a seven-cell reuse pattern at maximum capacity, a chipping rate of 64 Mchip/sec is sufficient to support this. Furthermore, given an average delay spread of 40 nsec, the resolvable number of paths is given by:

which translates to 2-3 resolvable paths by the receiver and dictates the size and complexity of the Rake receiver in the digital baseband hardware.

With a chipping rate of 64 Mchip/sec, a transmit bandwidth of 80 to 100 MHz will be required. Although this is a considerable amount of spectrum, this is amortized over large numbers of people using this spectrum simultaneously within multiple buildings. Considering that this bandwidth is designed to support full motion video and other multimedia network services for all users, this allocation of spectrum is not unreasonable given the level of service provided by the system, especially when compared to the spectrum allocated for existing systems by the National Television System Committee (NTSC) television standard.

For development and system verification for example, a baseband equivalent model for the transceiver system has been developed in the U.C. Berkeley Ptolemy simulation environment [Sheng, 4]. The schematic of the system utilizes a delay-locked loop keyed to the timing pilot tone to achieve synchronization/lock, and furthermore uses the pilot tone to provide an estimate of the channel impulse response. To simulate multipath effects, a baseband equivalent channel model has been developed from measured statistics [Sheng, 4]. This allows users to optimize the system for transmit power levels, number of parallel receivers, quantization levels in the receiver, etc.

As an example, the bit-error rate (BER) as a function of the number of users is shown in Figure 11—2, simulated under various conditions [Sheng, 5]. By Monte-Carlo methods, a worst-case (extreme fade) channel and a best-case channel were determined from the model, and then both channels were simulated with and without maximum-ratio Rake combining [Sheng, 4]. The benefits of the three-tap Rake receiver are apparent; under the worst-case fade condition, the Rake combiner provided a factor of up to 1000 improvement in BER over the uncompensated case. As the number of users increases, however, this not only degrades the base signal-to-noise ratio, but also degrades the accuracy of the channel estimate, reducing the effectiveness of the Rake combiner.

With high data rates and variable throughput requirements, developing the downlink has been of greatest importance, with CDMA providing an attractive means of both channel compensation and multiple access. The uplink, consisting of speech and pen input data, will require significantly lower data rates per user data rates (on the order of 32 Kbps), and due to near-far effects and the unsynchronized nature of the uplink signals, CDMA is not nearly as attractive. Instead, more conventional time-division multiple access (TDMA), frequency-hopped, or orthogonal frequency-division multiple access techniques are being explored for use in the uplink.

Monolithic RF Circuitry

Ostensibly, the linchpin of the wireless link lies in the development of the necessary radio-frequency components. In addition to the requirement of low power consumption, the analog RF circuitry is complicated by the need to operate at frequencies above 1 GHz. Due to spectral congestion and competition from existing services, it will be impossible to accommodate such a wideband system at any lower frequencies. Such circuitry has been traditionally dominated by designs using discrete gallium arsenide semiconductors (GaAs) or silicon bipolar transistors and stripline filters, which consume significant amounts of area on a circuit board and excessive amounts of power, especially when matching to standard impedance levels (typically, 50 ý).

First, the greatest power consumer in existing analog cellular is the transmitter. Since the transmit power must be scaled down as the cell radius is reduced, power consumed in the portable to drive the antenna drops correspondingly. Whereas existing cellular systems utilize 1 watt transmit power for RF links in 5 mile cells, a picocellular system with 5 meter cells only requires 0.1 to 1 milliwatt to maintain the link. The impact of this is tremendous; the traditional RF power amplifier is not needed, and transmit power becomes a small fraction of the overall system power consumption in a microcell or picocell environment.

Hence, power minimization of the remaining RF components becomes critical. Shown in Figure 11—3 is the block diagram of a conventional superheterodyne RF transceiver designed for picocell operation in the 902-928 MHz radio band [Sheng, 6]. Implemented using commercially available components, the power consumption for each active element in the transceiver is indicated. Even without the transmit power amplifier, the total consumption is impressive–1W overall, with 750 mW being consumed in the receiver. Furthermore, the component count is astronomical; over 200 passive and active devices are needed to implement the design, after taking into account external bypass, filter, and bias elements. Minimizing both the power and component count dictates the development of highly integrated analog technologies. From Figure 11—3, it is also apparent that the greatest gains are to be had from optimizing the receiver circuitry, given the complex chain of amplifiers, mixers, filters, oscillators, and Analog-to-Digital (A/D) converters required to implement it.

This part of the chapter will focus on the design and implementation of a single-chip, highly integrated receiver capable of operating in the 1 GHz frequency band and supporting a 64 Mchip/sec direct-sequence spread spectrum signal. To facilitate high integration levels, silicon CMOS is employed exclusively in the design.

As a demonstration, the RF amplifier design shown in Figure 11—4 has been fabricated and tested in a 1.2 micron technology (Sheng, 7]. The design is a two-stage transconductance-transresistance cascade, with the transresistance stage consisting of the tightly-coupled feedback loop formed by NMOS M2-M3. The presence of this feedback loop ensures that the circuit has no high-impedance nodes, thus achieving its broadband performance. Since the transconductance stage has gain gm1, the overall gain of the circuit is thus gm1/gm3, which can be shown to be process- and temperature-independent. The output buffers shown are needed to drive an off-chip filter stage, and are designed to be matched to 50W.

The measured performance characteristics of the amplifier are shown in Figure 11—4, including the frequency response of the circuit. The circuit was originally designed for use in a low-parasitic multichip module; however, for testing it became necessary to package the device in a 44-pin leadless chip carrier. The sharp peaking near the rolloff corner is due to the extra parasitics introduced by the package. The Transistor Level Circuit Simulator or Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for the amplifier with the package can be seen to fit quite well to measured values, and the SPICE simulation of the device in a multichip module is also shown. A version of this amplifier correcting for the package parasitics has been designed, and is fabricated as part of the integrated receiver circuit.

When sampling demodulators, a homodyne conversion method should be used that takes advantage of the fact that the underlying transmitted signal is inherently discrete-time [Sheng, 7]. If the incoming modulated RF signal at a carrier wc is subsampled at a frequency ws, where wc is assumed to be an integer multiple of ws, then the aliasing phenomenon intrinsic to the sampling operation will yield the required frequency conversion. This is akin to the passband sampling concept employed for many years by digital sampling oscilloscopes. Subsampling a passband signal is tantamount to a mixing operation. What was a complex series of active mixers and oscillators has been reduced to a single sampling operation, sampled at the Nyquist rate of the baseband signal. The hardware and power costs are now minimal: an accurate switch, implementable using standard MOS technologies, and a fixed-frequency crystal oscillator. A prototype demodulator has been fabricated to explore this concept. The modulated signal is a 20 kHz square wave riding on top of a 100 MHz carrier tone. The sampling rate is set to 1 MHz (100x subsampling ratio). Clearly, the sampled output is the recovered baseband envelope. The return to zero effect is a result of the sampling capacitors resetting during each cycle. Also, the slight curvature exhibited in the recovered baseband signal is due to the fact that wc is not a perfect integer multiple of ws. The frequency offset between the carrier frequency and the sampling rate is slight; in this case, it was measured to be 1.4 kHz.

In any case, the system design must take this phenomenon into account, since it is impossible to achieve zero offset. First, two sampling switches are employed to recover both the in-phase and quadrature signals. Thus, this frequency offset can be viewed as a slow rotation of the constellation in symbol space. Also, it is clear that the offset will be significantly smaller than the user symbol rate (1 MHz), given a typical frequency accuracy of 20 to 100 parts/million for crystal-based references. Thus, by employing an incoherent differential quadrature phase shift keying (DQPSK) digital modulation, the effects of the frequency offset can be nullified without the use of a carrier phase-locked recovery loop. Although a 3 dB signal-to-noise ratio (SNR) penalty is incurred by the incoherency, there are alternative strategies to recover this 3 dB that are far less expensive than carrier recovery, such as employing diversity antennas or error correction coding.

In order to meet the performance requirements for the spread-spectrum downlink, a sampling switch capable of handling a 1 GHz modulated signal and running at 128 MHz (twice the chipping rate) has been developed. The schematic of the demodulator is shown in Figure 11—5 [Sheng, 9]. First, to minimize the effects of switching noise and charge injection, a differential bottom-plate sampling topology is employed [Sheng, 8]. Second, the sampling capacitors must be able to track the 1 GHz modulated signal in order to sample the signal. Hence, the switches M1a,b and M2 must be carefully sized to ensure that the lowpass cutoff (formed by the on-resistance of the switches and the sampling capacitor) is well in excess of 1 GHz; otherwise, the incoming RF signal will be disastrously attenuated.

Furthermore, to achieve the 128 MHz switching performance, an extremely fast opamp is needed. In order to minimize the amount of static current in the opamp (and hence power), a unity-gain architecture is employed in which the sampling capacitor itself is used in the opamp feedback by opening switches M1a,b and closing switches M3a,b. This is has been shown to maximize the feedback factor for the closed-loop opamp [Sheng, 9]. Since settling time is proportional to 1/(Gmf)–where f is the feedback factor and Gm is the opamp transconductance gain (for a fixed settling time), increasing f translates to a decrease in the gain Gm. This correspondingly results in a minimum power solution to achieve the necessary settling time.

In this chapter, the design and implementation of a wireless system to support multimedia communications have been considered, with emphasis on a broadband downlink capable of supporting digital video. In particular, the development of integrated analog RF front-end and baseband digital interface circuitry, as well as the system simulations driving the design, have also been considered. An ultimate per-user data rate of 2 Mbps is the target. To achieve the required capacity, a picocellular system architecture is employed, using cells on the order of 5m in size.

In examining multiple access strategies for such an application, direct-sequence spread-spectrum or code-division multiple access possesses many advantages. For this particular system, a symbol rate of 1 Mbaud with a chipping rate of 64 Mchip/sec is used. For the spreading code, a Walsh-PN hybrid based on the existing IS-95 cellular standard is chosen. Beyond providing multiple access, the ability to resolve multiple arrivals and detect adjacent channels in the digital baseband circuitry also affords many benefits that other systems (such as time-division or frequency-hop) cannot so easily provide. Taking advantage of the broadcast mode transmission of the downlink, each cell is keyed to a pseudorandom pilot tone which tremendously simplifies timing recovery and detection in the mobile.

Since portability places severe constraints on the size and weight of the terminal itself, power is at a premium as the batteries simply cannot provide much power on a continuous basis without expending an inordinate amount of weight, or an extremely short usable lifetime between rechargings. Thus, low-power digital systems design becomes of paramount importance. Through optimized circuit design strategies, reduced supply-voltage operation and architectural techniques (such as parallelism and pipelining the power consumed in the terminal) can be reduced dramatically.

Lastly, exploiting dedicated parallel and pipelined techniques, a low-power spread-spectrum receiver can be designed in spite of the tremendous chipping rate of the system (64 Mchip/sec). By scaling the supply voltage, and employing multiple supplies into the chip, optimal voltages can be chosen to meet throughput requirements and minimize power consumption in the baseband digital logic.

This chapter discussed wireless design considerations (spread spectrum, microwave, and the design and implementation of wireless systems to support multimedia communications, etc.). The next chapter opens up Part III, "Planning For High-Speed Cabling Systems," by taking a thorough look at high-speed real-time data compression and how to plan for higher-speed cabling systems.

[1] Joel B Wood, "The Wireless LANs Page," The Ohio Sate University Computer and Information Science Deapartment, 395 Dreese Laboratories, 2015 Neil Avenue, Columbus, Ohio 43210-1277, 1995, pp. 1—3.

[2] Samuel Sheng, Randy Allmon, Lapoe Lynn, Ian O’Donnell, Kevin Stone, and Robert Brodersen, "A Monolithic CMOS Radio System for Wideband CDMA Communications," Department of EECS, 231 Cory Hall #1770, U.C. Berkeley Berkeley, CA 94720 USA, 1997, p. 2.