"Getting to 10 Gbits/s on twisted-pair wiring is all about using existing bandwidth more efficiently," Raghaven said. "First, we had to implement an encoding scheme that gave us more effective bits per baud. That had to be coupled with much more aggressive forward error correction to improve the noise margin."
"Second, we needed to significantly improve both the bandwidth and the linearity of the mixed-signal section of the chip. Third, we had to dramatically increase the throughput of the digital signal-processing function, both to keep up with the increased bit rate and to handle the more aggressive algorithms."
The chip, fabricated in 130-nanometer mixed-signal CMOS, connects directly to a standard RJ-45 connector on the media side and to a Xaui port on the system side. The device includes a proprietary PHY and DSP functions to do the heavy lifting.
The company chose 6-bit/baud quadrature amplitude modulation, leveraging QAM's efficient bandwidth utilization and computability. The modulation technique is backed up by a modified multidimensional trellis forward error correction (FEC) algorithm.