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Agilent Drives Out SAN Errors: Page 2 of 3

However, EDC isn't an industry standard yet -- the EDC algorithm will work only with Agilent's own chips, for now. Agilent says it expects EDC to become a standard through the InterNational Committee for Information Technology Standards (INCITS) T10 committee, which oversees SCSI specifications. A vote by the T10 committee on whether to approve EDC as a standard is scheduled for November.

Ottem says EDC becomes even more important as Fibre Channel speeds increase to 4 and 10 Gbit/s in the coming years . The overhead attributable to EDC is only 1 percent, Agilent says -- far less than with systems that implement error correction in higher-layer software.

The HPFC-5600 chip supports both 1- and 2-Gbit/s Fibre Channel operation, and is backward-compatible with previous generations of Agilent's Tachyon controllers. The HPFC-5600 interfaces to either PCI or PCI-X buses, and supports both 32- and 64-bit formats. It's available now in samples; Agilent expects volume production to start in the first quarter of 2004, which is when it plans to announce pricing.

Agilent will pitch the new FC chip to enterprise storage array companies. Agilent's storage customers include EMC Corp. (NYSE: EMC), Hewlett-Packard Co. (NYSE: HPQ), Hitachi Ltd. (NYSE: HIT; Paris: PHA), IBM Corp. (NYSE: IBM), and LSI Logic Storage Systems Inc.

Also today, Agilent announced the HDMP-0528, an eight-port port bypass circuit (PBC) device for serial Fibre Channel Arbitrated Loop (FC-AL) signals within storage subsystems. One of the basic functions of the PBC is to let individual disk drives be added or removed from an array without affecting the operation of the rest of the system.